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AD9530 Datasheet(PDF) 1 Page - Analog Devices |
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AD9530 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 41 page  4 CML Output, Low Jitter Clock Generator with an Integrated 5.4 GHz VCO Data Sheet AD9530 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Fully integrated, ultralow noise phase-locked loop (PLL) 4 differential, 2.7 GHz common-mode logic (CML) outputs 2 differential reference inputs with programmable internal termination options <232 fs rms absolute jitter (12 kHz to 20 MHz) with a non- ideal reference and 8 kHz loop bandwidth <100 fs rms absolute jitter (12 kHz to 20 MHz) with an 80 kHz loop bandwidth and low jitter input reference clock Supports low loop bandwidths for jitter attenuation Manual switchover Single 2.5 V typical supply voltage 48-lead, 7 mm × 7 mm LFCSP APPLICATIONS 40 Gbps/100 Gbps optical transport network (OTN) line side clocking Clocking of high speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) Data communications GENERAL DESCRIPTION The AD9530 is a fully integrated PLL and distribution supporting, clock cleanup, and frequency translation device for 40 Gbps/ 100 Gbps OTN applications. The internal PLL can lock to one of two reference frequencies to generate four discrete output frequencies up to 2.7 GHz. The AD9530 features an internal 5.11 GHz to 5.4 GHz, ultralow noise voltage controlled oscillator (VCO). All four outputs are individually divided down from the internal VCO using two high speed VCO dividers (the Mx dividers) and four individual 8-bit channel dividers (the Dx dividers). The high speed VCO dividers offer fixed divisions of 2, 2.5, 3, and 3.5 for wide coverage of possible output frequencies. The AD9530 is configurable for loop bandwidths <15 kHz to attenuate reference noise. The AD9530 is available in a 48-lead LFCSP and operates from a single 2.5 V typical supply voltage. The AD9530 operates over the extended industrial temperature range of −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM REFB PLL R DIVIDER (1 TO 255) M1 DIVIDER ÷2, ÷2.5, ÷3, ÷3.5 M2 DIVIDER ÷2, ÷2.5, ÷3, ÷3.5 SERIAL PORT AND CONTROL LOGIC AD9530 REFA SDIO REFA REFB REF_SEL OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 D1 DIVIDER (1 TO 255) D2 DIVIDER (1 TO 255) D3 DIVIDER (1 TO 255) D4 DIVIDER (1 TO 255) SDO SCLK LD CML 50Ω SOURCE TERMINATED 2.7GHz MAX 800MHz MAX CS Figure 1. |
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