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LTC6948 Datasheet(PDF) 23 Page - Analog Devices |
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LTC6948 Datasheet(HTML) 23 Page - Analog Devices |
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23 / 38 page  LTC6948 23 6948fa For more information www.linear.com/LTC6948 operaTion Table 15. Serial Port Register Contents ADDR MSB [6] [5] [4] [3] [2] [1] LSB R/W DEFAULT h00 * * UNLOCK ALCHI ALCLO LOCK THI TLO R h01 * * x[5] x[4] x[3] x[2] x[1] x[0] R/W h04 h02 PDALL PDPLL PDVCO PDOUT PDFN MTCAL OMUTE POR R/W h06 h03 ALCEN ALCMON ALCCAL ALCULOK AUTOCAL AUTORST DITHEN INTN R/W h3E h04 BD[3] BD[2] BD[1] BD[0] CPLE LDOEN LDOV[1] LDOV[0] R/W h47 h05 SEED[7] SEED[6] SEED[5] SEED[4] SEED[3] SEED[2] SEED[1] SEED[0] R/W h11 h06 RD[4] RD[3] RD[2] RD[1] RD[0] * ND[9] ND[8] R/W h08 h07 ND[7] ND[6] ND[5] ND[4] ND[3] ND[2] ND[1] ND[0] R/W hFA h08 * * NUM[17] NUM[16] NUM[15] NUM[14] NUM[13] NUM[12] R/W h3F h09 NUM[11] NUM[10] NUM[9] NUM[8] NUM[7] NUM[6] NUM[5] NUM[4] R/W hFF h0A NUM[3] NUM[2] NUM[1] NUM[0] * * RSTFN CAL R/W hF0 h0B BST FILT[1] FILT[0] RFO[1] RFO[0] OD[2] OD[1] OD[0] R/W hF9 h0C LKWIN[2] LKWIN[1] LKWIN[0] LKCT[1] LKCT[0] CP[2] CP[1] CP[0] R/W h4F h0D CPCHI CPCLO CPMID CPINV CPWIDE CPRST CPUP CPDN R/W hE4 h0E REV[3] REV[2] REV[1] REV[0] PART[3] PART[2] PART[1] PART[0] R hxx† *unused †varies depending on version Multidrop Configuration Several LTC6948s may share the serial bus. In this mul- tidrop configuration, SCLK, SDI, and SDO are common betweenallparts.Theserialbusmastermustuseaseparate CS for each LTC6948 and ensure that only one device has CS asserted at any time. It is recommended to attach a high value resistor to SDO to ensure the line returns to a known level during Hi-Z states. Serial Port Registers The memory map of the LTC6948 may be found below in Table 15, with detailed bit descriptions found in Table 16. The register address shown in hexadecimal format under the ADDR column is used to specify each register. Each register is denoted as either read-only (R) or read-write (R/W). The register’s default value on device power-up or after a reset is shown at the right. The read-only register at address h00 is used to determine different status flags. These flags may be instantly output on the STAT pin by configuring register h01. See STAT Output section that follows for more information. The read-only register at address h0E is a ROM byte for device identification. STAT Output The STAT output pin is configured with the x[5:0] bits of register h01. These bits are used to bit-wise mask, or enable, the corresponding status flags of status register h00, according to Equation 2. The result of this bit-wise Boolean operation is then output on the STAT pin. STAT = OR (Reg00[5:0] AND Reg01[5:0]) (2) or, expanded, STAT = (UNLOCK AND x[5]) OR (ALCHI AND x[4]) OR (ALCLO AND x[3]) OR (LOCK AND x[2]) OR (THI AND x[1]) OR (TLO AND x[0]) For example, if the application requires STAT to go high whenever the ALCHI, ALCLO, or THI flags are set, then x[4], x[3], and x[1] should be set to 1, giving a register value of h1A. |
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