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LTC6948 Datasheet(PDF) 28 Page - Analog Devices |
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LTC6948 Datasheet(HTML) 28 Page - Analog Devices |
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28 / 38 page ![]() LTC6948 28 6948fa For more information www.linear.com/LTC6948 applicaTions inForMaTion Loop Filter Component Selection Now set loop filter resistor RZ and charge pump current ICP. Because the KVCO varies over the VCO’s frequency range, using the KVCO geometric mean gives good results: KVCO = 3.843 •109 • 0.047 • 0.07 = 220.4MHz / V Using an ICP of 5.6mA, the FracNWizard uses Equation 12 to determine RZ: RZ = 2• π •150k •76 5.6m•220.4M RZ = 58.0Ω For the 4th order Filter 3, FracNWizard uses modified Equations 13 and 14 to calculate CI, CP: CI = 4.5 2• π •150k •58 = 82.3nF CP = 1 10.5• π •150k •58 = 3.5nF FracNWizard calculates R1, L1, and C2 to be: R1 = 58.0Ω C2 = 2.3nF L1 = 7.8µH Status Output Programming This example will use the STAT pin to alert the system whenever the LTC6948 generates a fault condition. Pro- gram x[5], x[4], x[3], x[1], x[0] = 1 to force the STAT pin high whenever any of the UNLOCK, ALCHI, ALCLO, THI, or TLO flags asserts: Reg01 = h3B Power Register Programming For correct PLL operation all internal blocks should be enabled. OMUTE may remain asserted (or the MUTE pin held low) until programming is complete. For OMUTE = 1: Reg02 = h02 VCO ALC, AUTOCAL, and AUTORST Programming Set the ALC options (ALCMON = ALCULOK = ALCCAL = 1), the auto reset options (AUTOCAL = AUTORST = 1), and the Δ∑ modulator modes (DITHEN = 1, INTN = 0) at the same time: Reg03 = h7E The ALC will only be active during a calibration cycle or when the loop is unlocked, but the ALCHI and ALCLO statusconditionswillbemonitoredcontinuously.TheVCO will be calibrated and the Δ∑ modulator will be reset at the end of the SPI write communication burst (assuming an auto-increment write is used to write all registers). LDO Programming Use Table 13 and fPFD = 50MHz to determine V(LDO) and LDOV[1:0]: V(LDO) = 2.3V and LDOV[1:0] = 2 Use LDOV[1:0], LDOEN = 1 to enable the LDO, and the previously determined BD[3:0] value to set Reg04. CPLE should be set to 1 to reduce in-band noise and spurious due to the Δ∑ modulator: Reg04 = h5E SEED Programming The SEED[7:0] value is used to initialize the Δ∑ modulator dither circuitry. Use the default value: Reg05 = h11 |
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