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C161 Datasheet(PDF) 179 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 179 Page - Infineon Technologies AG |
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179 / 400 page  &3, 7KH([WHUQDO%XV ,QWHUIDFH User’s Manual 9-15 1999-08 Programmable Memory Tri-State Time The C161PI allows the user to adjust the time between two subsequent external accesses to account for the tri-state time of the external device. The tri-state time defines, when the external device has released the bus after deactivation of the read command (RD). Figure 9-8 Memory Tri-State Time The output of the next address on the external bus can be delayed for a memory or peripheral, which needs more time to switch off its bus drivers, by introducing a wait state after the previous bus cycle (see figure above). During this memory tri-state time wait state, the CPU is not idle, so CPU operations will only be slowed down if a subsequent external instruction or data fetch operation is required during the next instruction cycle. The memory tri-state time waitstate requires one CPU clock (2 TCL) and is controlled via the MTTCx bits of the BUSCON registers. A waitstate will be inserted, if bit MTTCx is ‘0’ (default after reset). Note: External bus cycles in multiplexed bus modes implicitly add one tri-state time waitstate in addition to the programmable MTTC waitstate. |
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