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C161 Datasheet(PDF) 178 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 178 Page - Infineon Technologies AG |
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178 / 400 page  &3, 7KH([WHUQDO%XV ,QWHUIDFH User’s Manual 9-14 1999-08 Programmable Memory Cycle Time The C161PI allows the user to adjust the controller’s external bus cycles to the access time of the respective memory or peripheral. This access time is the total time required to move the data to the destination. It represents the period of time during which the controller’s signals do not change. Figure 9-7 Memory Cycle Time The external bus cycles of the C161PI can be extended for a memory or peripheral, which cannot keep pace with the controller’s maximum speed, by introducing wait states during the access (see figure above). During these memory cycle time wait states, the CPU is idle, if this access is required for the execution of the current instruction. The memory cycle time wait states can be programmed in increments of one CPU clock (2 TCL) within a range from 0 to 15 (default after reset) via the MCTC fields of the BUSCON registers. 15-<MCTC> waitstates will be inserted. |
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