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C161 Datasheet(PDF) 180 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 180 Page - Infineon Technologies AG |
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180 / 400 page  &3, 7KH([WHUQDO%XV ,QWHUIDFH User’s Manual 9-16 1999-08 Read/Write Signal Delay The C161PI allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals. The read/write delay controls the time between the falling edge of ALE and the falling edge of the command. Without read/ write delay the falling edges of ALE and command(s) are coincident (except for propagation delays). With the delay enabled, the command(s) become active half a CPU clock (1 TCL) after the falling edge of ALE. The read/write delay does not extend the memory cycle time, and does not slow down the controller in general. In multiplexed bus modes, however, the data drivers of an external device may conflict with the C161PI’s address, when the early RD signal is used. Therefore multiplexed bus cycles should always be programmed with read/write delay. The read/write delay is controlled via the RWDCx bits in the BUSCON registers. The command(s) will be delayed, if bit RWDCx is ‘0’ (default after reset). Figure 9-9 Read/Write Signal Duration Control 1) The data drivers from the previous bus cycle should be disabled when the RD signal becomes active. |
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