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C161 Datasheet(PDF) 181 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 181 Page - Infineon Technologies AG |
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181 / 400 page  &3, 7KH([WHUQDO%XV ,QWHUIDFH User’s Manual 9-17 1999-08 9.4 READY Controlled Bus Cycles For situations, where the programmable waitstates are not enough, or where the response (access) time of a peripheral is not constant, the C161PI provides external bus cycles that are terminated via a READY input signal (synchronous or asynchronous). In this case the C161PI first inserts a programmable number of waitstates (0...7) and then monitors the READY line to determine the actual end of the current bus cycle. The external device drives READY low in order to indicate that data have been latched (write cycle) or are available (read cycle). Figure 9-10 READY Controlled Bus Cycles The READY function is enabled via the RDYENx bits in the BUSCON registers. When this function is selected (RDYENx = ‘1’), only the lower 3 bits of the respective MCTC bit field define the number of inserted waitstates (0...7), while the MSB of bit field MCTC selects the READY operation: MCTC.3=‘0’: Synchronous READY, i.e. the READY signal must meet setup and hold times. MCTC.3=‘1’: Asynchronous READY, i.e. the READY signal is synchronized internally. |
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