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C161 Datasheet(PDF) 195 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 195 Page - Infineon Technologies AG |
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195 / 400 page  &3, 7KH*HQHUDO 3XUSRVH 7LPHU8QLWV User’s Manual 10-3 1999-08 10.1.1 GPT1 Core Timer T3 The core timer T3 is configured and controlled via its bitaddressable control register T3CON. *) For the effects of bits T3UD and T3UDE refer to the direction table below. T3CON Timer 3 Control Register SFR (FF42 H/A1H) Reset value: 0000 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - --- - T3 OTL T3 OE T3 UDE T3 UD T3R T3M T3I - - - - - rwh rw rw rw rw rw rw Bit Function T3I Timer 3 Input Selection Depends on the operating mode, see respective sections. T3M Timer 3 Mode Control (Basic Operating Mode) 000: Timer Mode 001: Counter Mode 010: Gated Timer with Gate active low 011: Gated Timer with Gate active high 100: Reserved. Do not use this combination. 101: Reserved. Do not use this combination. 110: Incremental Interface Mode 111: Reserved. Do not use this combination. T3R Timer 3 Run Bit 0: Timer / Counter 3 stops 1: Timer / Counter 3 runs T3UD Timer 3 Up / Down Control *) T3UDE Timer 3 External Up/Down Enable *) T3OE Alternate Output Function Enable 0: Alternate Output Function Disabled 1: Alternate Output Function Enabled T3OTL Timer 3 Output Toggle Latch Toggles on each overflow / underflow of T3. Can be set or reset by software. |
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