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C161 Datasheet(PDF) 191 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 191 Page - Infineon Technologies AG |
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191 / 400 page  &3, 7KH([WHUQDO%XV ,QWHUIDFH User’s Manual 9-27 1999-08 9.6 EBC Idle State When the external bus interface is enabled, but no external access is currently executed, the EBC is idle. As long as only internal resources (from an architecture point of view) like IRAM, GPRs or SFRs, etc. are used the external bus interface does not change (see table below). Accesses to on-chip X-Peripherals are also controlled by the EBC. However, even though an X-Peripheral appears like an external peripheral to the controller, the respective accesses do not generate valid external bus cycles. Due to timing constraints address and write data of an XBUS cycle are reflected on the external bus interface (see table below). The „address“ mentioned above includes PORT1, Port 4, BHE and ALE which also pulses for an XBUS cycle. The external CS signals on Port 6 are driven inactive (high) because the EBC switches to an internal XCS signal. The external control signals (RD and WR or WRL/WRH if enabled) remain inactive (high). Table 9-7 Status Of The External Bus Interface During Ebc Idle State Pins Internal accesses only XBUS accesses PORT0 Tristated (floating) Tristated (floating) for read accesses XBUS write data for write accesses PORT1 Last used external address (if used for the bus interface) Last used XBUS address (if used for the bus interface) Port 4 Last used external segment address (on selected pins) Last used XBUS segment address (on selected pins) Port 6 Active external CS signal corresponding to last used address Inactive (high) for selected CS signals BHE Level corresponding to last external access Level corresponding to last XBUS access ALE Inactive (low) Pulses as defined for X-Peripheral RD Inactive (high) Inactive (high) WR/WRL Inactive (high) Inactive (high) WRH Inactive (high) Inactive (high) |
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