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C161 Datasheet(PDF) 190 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 190 Page - Infineon Technologies AG |
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190 / 400 page  &3, 7KH([WHUQDO%XV ,QWHUIDFH User’s Manual 9-26 1999-08 Note: RP0H cannot be changed via software, but rather allows to check the current configuration. Precautions and Hints • The ext. bus interface is enabled as long as at least one of the BUSCON registers has its BUSACT bit set. • PORT1 will output the intra-segment addr. as long as at least one of the BUSCON registers selects a demultiplexed external bus, even for multiplexed bus cycles. • Not all addr. windows defined via registers ADDRSELx may overlap each other. The operation of the EBC will be unpredictable in such a case. See chapter „Address Window Arbitration“. • The addr. windows defined via registers ADDRSELx may overlap internal addr. areas. Internal accesses will be executed in this case. • For any access to an internal addr. area the EBC will remain inactive (see EBC Idle State). RP0H Reset Value of P0H SFR (F108 H/84H) Reset value: - - XX H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKCFG SALSEL CSSEL WRC rh rh rh rh Bit Function WRC Write Configuration 0: Pins WR and BHE operate as WRL and WRH signals 1: Pins WR and BHE operate as WR and BHE signals CSSEL Chip Select Line Selection (Number of active CS outputs) 00: 3 CS lines: CS2...CS0 01: 2 CS lines: CS1...CS0 10: No CS lines at all 11: 5 CS lines: CS4...CS0 (Default without pulldowns) SALSEL Segment Address Line Selection (Nr. of active segment addr. outputs) 00: 4-bit segment address: A19...A16 01: No segment address lines at all 10: 7-bit segment address: A22...A16 11: 2-bit segment address: A17...A16 (Default without pulldowns) CLKCFG Clock Generation Mode Configuration These pins define the clock generation mode, i.e. the mechanism how the internal CPU clock is generated from the externally applied (XTAL1) input clock. |
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