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C161 Datasheet(PDF) 186 Page - Infineon Technologies AG

Part # C161
Description  16-Bit Single-Chip Microcontroller
PDF  400 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

C161 Datasheet(HTML) 186 Page - Infineon Technologies AG

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User’s Manual
9-22
1999-08
with the bus configuration selected via PORT0.
Bit
Function
MCTC
Memory Cycle Time Control (Number of memory cycle time wait states)
0000: 15 waitstates
. . .
(Number = 15 - <MCTC>)
1111: No waitstates
Note: The definition of bitfield MCTCx changes if RDYENx = ’1’
(see page 17)
RWDCx
Read/Write Delay Control for BUSCONx
0:
With rd/wr delay: activate command 1 TCL after falling edge of ALE
1:
No rd/wr delay: activate command with falling edge of ALE
MTTCx
Memory Tristate Time Control
0:
1 waitstate
1:
No waitstate
BTYP
External Bus Configuration
00:
8-bit Demultiplexed Bus
01:
8-bit Multiplexed Bus
10:
16-bit Demultiplexed Bus
11:
16-bit Multiplexed Bus
Note: For BUSCON0 BTYP is defined via PORT0 during reset.
ALECTLx
ALE Lengthening Control
0:
Normal ALE signal
1:
Lengthened ALE signal
BUSACTx
Bus Active Control
0:
External bus disabled
1:
External bus enabled within respective address window (ADDRSEL)
RDYENx
READY Input Enable
0:
External bus cycle is controlled by bit field MCTC only
1:
External bus cycle is controlled by the READY input signal
CSRENx
Read Chip Select Enable
0:
The CS signal is independent of the read command (RD)
1:
The CS signal is generated for the duration of the read command
CSWENx
Write Chip Select Enable
0:
The CS signal is independent of the write cmd. (WR,WRL,WRH)
1:
The CS signal is generated for the duration of the write command



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