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C161 Datasheet(PDF) 192 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 192 Page - Infineon Technologies AG |
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192 / 400 page  &3, 7KH([WHUQDO%XV ,QWHUIDFH User’s Manual 9-28 1999-08 9.7 The XBUS Interface The C161PI provides an on-chip interface (the XBUS interface), via which integrated customer/application specific peripherals can be connected to the standard controller core. The XBUS is an internal representation of the external bus interface, i.e. it is operated in the same way. For each peripheral on the XBUS (X-Peripheral) there is a separate address window controlled by a register pair XBCONx/XADRSx (similar to registers BUSCONx and ADDRSELx). As an interface to a peripheral in many cases is represented by just a few registers, the registers partly select smaller address windows than the standard ADDRSEL registers. As the register pairs control integrated peripherals rather than externally connected ones, most of them are fixed by mask programming rather than being user programmable. X-Peripheral accesses provide the same choices as external accesses, so these peripherals may be bytewide or wordwide. Because the on-chip connection can be realized very efficient and for performance reasons X-Peripherals are only implemented with a separate address bus, i.e. in demultiplexed bus mode. Interrupt nodes are provided for X-Peripherals to be integrated. Note: If you plan to develop a peripheral of your own to be integrated into a C161PI device to create a customer specific version, please ask for the specification of the XBUS interface and for further support. Enabling of XBUS Peripherals After reset all on-chip XBUS peripherals are disabled. In order to be usable an XBUS peripheral must be enabled via the global enable bit XPEN in register SYSCON. The following table summarizes the XBUS peripherals and also the number of waitstates which are used when accessing the respective peripheral. Table 9-8 XBUS Peripherals in the C161PI Associated XBUS Peripheral Waitstates I 2C0 XRAM 2 KByte 0 |
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