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Table 10-31. Pseudorandom Pattern Generation

BERT.PCR Register

BERT.CR

PATTERN TYPE

PTF[4:0]

(hex)

PLF[4:0]

(hex)

PTS

QRSS

BERT.

PCR

BERT.

SPR2

BERT.

SPR1

TPIC,

RPIC

9-1 O.153 (511 type)

0x0408

0xFFFF

11-1 O.152 and O.153

(2047 type)

0x080A

0xFFFF

15-1 O.151

0x0D0E

0xFFFF

20-1 O.153

0x1013

0xFFFF

20-1 O.151 QRSS

0x0253

0xFFFF

23-1 O.151

0x1116

0xFFFF

Table 10-32. Repetitive Pattern Generation

BERT.PCR Register

PATTERN TYPE

PTF[4:0]

(hex)

PLF[4:0]

(hex)

PTS

QRSS

BERT.

PCR

BERT.

SPR2

BERT.

SPR1

all 1s

0x0020

0xFFFF

all 0s

0x0020

0xFFFF

0xFFFE

alternating 1s and 0s

0x0021

0xFFFF

0xFFFE

double alternating and 0s

0x0023

0xFFFF

0xFFFC

3 in 24

0x0037

0xFF20

0x0022

1 in 16

0x002F

0xFFFF

0x0001

1 in 8

0x0027

0xFFFF

0xFF01

1 in 4

0x0023

0xFFFF

0xFFF1

After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one

transition on BERT.CR.TNPL and BERT.CR.RNPL

Monitoring the BERT requires reading the BERT.SR Register which contains the Bit Error Count (BEC) bit and the

Out of Synchronization (OOS) bit. The BEC bit will be one when the bit error counter is one or more. The OOS will

be one when the receive pattern generator is not synchronized to the incoming pattern, which will occur when it

receives a minimum 6 bit errors within a 64 bit window. The Receive BERT Bit Count Register (BERT.RBCR1) and

the Receive BERT Bit Error Count Register (BERT.RBECR1) will be updated upon the reception of a Performance

Monitor Update signal (e.g. BERT.CR.LPMU). This signal will update the registers with the values of the counter

since the last update and will reset the counters. See Section 10.4.5 for more details of the PMU.

10.11.4 Receive Pattern Detection

When the Receive BERT is enabled it can be used as an off-line monitor. The incoming datastream flows to the

receive BERT as well as the DS3/E3 backplane.

The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming

pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or

bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating

polynomial x

n + xy + 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is

bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is

the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if

the next 14 bits are all zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will

be forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern programmed, pattern detection

performs either PRBS synchronization or repetitive pattern synchronization.

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