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DS3172 Datasheet(PDF) 111 Page - Dallas Semiconductor |
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DS3172 Datasheet(HTML) 111 Page - Dallas Semiconductor |
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111 / 232 page ![]() DS3171/DS3172/DS3173/DS3174 111 of 231 10.12 LIU – Line Interface Unit 10.12.1 General Description The line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3 or E3 lines. Each LIU has independent receive and transmit paths and a built-in jitter attenuator. Refer to Figure 10-31 for the location within the DS3174, 3,2,1 device of the LIU. Figure 10-31. LIU Functional Diagram DS3/E3 Transmit LIU IEEE P1149.1 JTAG Test Access Port Microprocessor Interface HDLC FEAC DS3 / E3 Transmit Formatter DS3 / E3 Receive Framer Trail Trace Buffer DS3/E3 Receive LIU TAIS TUA1 Clock Rate Adapter TX BERT RX BERT UA1 GEN B3ZS/ HDB3 Encoder B3ZS/ HDB3 Decoder 10.12.2 Features · Each Port Independently Configurable · Perform Receive Clock/Data Recovery and Transmit Waveshaping · Jitter Attenuators can be Placed in Either the Receive or Transmit Paths · Interface to 75 W Coaxial Cable at Lengths Up to 380 meters (DS3), 440 meters (E3) · Use 1:2 Transformers on TX and RX · Require Minimal External Components · Local and Remote Loopbacks 10.12.2.1 Transmitter · Gapped clock capable up to 52MHz · Wide 50 ±20% transmit clock duty cycle · Clock inversion for glueless interfacing · Unframed all-ones generator (E3 AIS) · Line build-out (LBO) control · Tri-state line driver outputs support protection switching applications · Per-channel power-down control · Output driver monitor 10.12.2.2 Receiver · AGC/equalizer block handles from 0 to 15dB of cable loss · Loss-of-lock (LOL) PLL status indication · Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp · Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775) · Clock inversion for glueless interfacing · Per-channel power-down control |
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