DS3172 datasheet(113/232 Pages) DALLAS

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The transmitter line driver can be disabled and the TXPn and TXNn outputs tri-stated by asserting the LTS

configuration bit (PORT.CR2.LTS). Powering down the transmitter through the TPD configuration bit (CPU bus

mode) also tri-states the TXPn and TXNn outputs.

10.12.4.3 Interfacing to the Line

The transmitter interfaces to the outgoing DS3/E3 coaxial cable (75

W) through a 2:1 step-down transformer

connected to the TXPn and TXNn pins. Figure 1-1 shows the arrangement of the transformer and other

recommended interface components. Table 10-33 specifies the required characteristics of the transformer.

10.12.4.4 Transmit Driver Monitor

If the transmit driver monitor detects a faulty transmitter, it sets the PORT.SR.TDM status bit. When the transmitter

is tri-stated, the transmit driver monitor is also disabled. The transmitter is declared to be faulty when the

transmitter outputs see a load of less than ~25

10.12.4.5 Transmitter Power-Down

To minimize power consumption when the transmitter is not being used, assert the PORT.CR1.PD configuration

bit. When the transmitter is powered down, the TXPn and TXNn pins are put in a high-impedance state and the

transmit amplifiers are powered down.

10.12.4.6 Transmitter Jitter Generation (Intrinsic)

The transmitter meets the jitter generation requirements of all applicable standards, with or without the jitter

attenuator enabled.

10.12.4.7 Transmitter Jitter Transfer

Without the jitter attenuator enabled in the transmit side, the transmitter passes jitter through unchanged. With the

jitter attenuator enabled in the transmit side, the transmitter meets the jitter transfer requirements of all applicable

telecommunication standards. See Table 4-1.

10.12.5 Receiver

10.12.5.1 Interfacing to the Line

The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the receiver interfaces to the

incoming coaxial cable (75

W) through a 1:2 step-up transformer. Figure 1-1 shows the arrangement of the

transformer and other recommended interface components. Table 10-33 specifies the required characteristics of

the transformer. Figure 10-32 shows a general overview of the LIU block. The receiver expects the incoming signal

to be in B3ZS- or HDB3-coded AMI format.

Table 10-33. Transformer Characteristics

PARAMETER

VALUE

Turns Ratio

1:2ct

±2%

Bandwidth 75

0.250MHz to 500MHz (typ)

Primary Inductance

mH (min)

Leakage Inductance

0.12

mH (max)

Interwinding Capacitance

10pF (max)

Isolation Voltage

1500VRMS (min)

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