DS3172 datasheet(115/232 Pages) DALLAS

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For E3 LOS Assertion:

The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or equal to a signal

level approximately 24dB below nominal, and mutes the data coming out of the clock and data recovery block.

(24dB below nominal in the “tolerance range” of G.775, where LOS may or may not be declared.)

For E3 LOS Clear:

The ALOS detector in the AGC/equalizer block detects that the incoming signal is greater than or equal to a signal

level approximately 18dB below nominal, and enables data to come out of the CDR block. (18dB is in the

“tolerance range” of G.775, where LOS may or may not be declared.)

10.12.5.6 Receiver Power-Down

To minimize power consumption when the receiver is not being used, write a one to the PORT.CR1.PD bit. When

the receiver is powered down, the RCLKOn pin is tri-stated. In addition, the RXPn and RXNn pins become high

impedance.

10.12.5.7 Receiver Jitter Tolerance.

The receiver exceeds the input jitter tolerance requirements of all applicable telecommunication standards in Table

4-1. See Figure 10-33.

Figure 10-33. Receiver Jitter Tolerance

100

10k

100k

60k

22.3k

2.3k

669

0.1

1.0

300k

800k

300

0.1

0.15

0.3

1.5

E3 G.823

DS3 GR-499 Cat II

DS3 GR-499 Cat I

DS317x JITTER TOLERANCE

STS-1 GR253

FREQUENCY (Hz)

DS3172 Datasheet(PDF) 115 Page - Dallas Semiconductor