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Figure 10-30. Repetitive Pattern Synchronization State Diagram

Sync

Match

Verify

1 bit error

Pattern Matches

10.11.4.3 Receive Pattern Monitoring

Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts

the incoming bits. An Out Of Synchronization (OOS) condition is declared when the synchronization state machine

is not in the “Sync” state. An OOS condition is terminated when the synchronization state machine is in the “Sync”

state.

Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. If they

do not match, a bit error is declared, and the bit error and bit counts are incremented. If they match, only the bit

count is incremented. The bit count and bit error count are not incremented when an OOS condition exists.

10.11.5 Transmit Pattern Generation

Pattern Generation generates the outgoing test pattern, and passes it onto Error Insertion. The transmit pattern

generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant

bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial x

n + xy + 1), the

feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and

y are individually programmable (1 to 32). The output of the receive pattern generator is the feedback. If QRSS is

enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if the next 14 bits are all

zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will be forced to one if bits

1 through 31 are all zeros. When a new pattern is loaded, the pattern generator is loaded with a seed/pattern value

before pattern generation starts. The seed/pattern value is programmable (0 – 2

n - 1).

10.11.5.1 Transmit Error Insertion

Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time or at a rate of

one out of every 10

n bits. The value of n is programmable (1 to 7 or off). Single bit error insertion can be initiated

from the microprocessor interface, or by the manual error insertion input (TMEI). The method of single error

insertion is programmable (register or input). If pattern inversion is enabled, the data stream is inverted before the

overhead/stuff bits are inserted. Pattern inversion is programmable (on or off).

DS3172 Datasheet(PDF) 110 Page - Dallas Semiconductor