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Bit 9: BERT Enable (BENA). This bit is used to enable the BERT logic. The BERT pattern will be the payload data

replacing the data from the TSERn pin.

0 = BERT logic disabled and powered down

1 = BERT logic enabled

Bit 7: Transmit Manual Error Insert (TMEI) This bit is used to insert errors in all error insertion logic configured to

use this bit when PORT.CR1.MEIM=0. The error(s) will be inserted when this bit is toggled low to high.

Bit 6: Transmit Manual Error Insert Mode (MEIM). These bits select the method transmit manual error insertion

for this port for error generators configured to use the external TMEI signal. The global updates are controlled by

the GL.CR1.MEIMS bit.

0 = Port software update via PORT.CR1.TMEI

1 = Global update source

Bit 4: Performance Monitor Update Mode (PMUM). These bits select the method of updating the performance

monitor registers. The global updates are controlled by the GL.CR1.GPM[1:0] bits.

0 = Port software update

1 = Global update

Bit 3: Performance Monitor Register Update (PMU) This bit is used to update all of the performance monitor

registers configured to use this bit when PORT.CR1.PMUM=0. The performance registers configured to use this

signal will be updated with the latest count value and the counters reset when this bit is toggled low to high. The bit

should remain high until the performance register update status bit (PORT.SR.PMS) goes high, then it should be

brought back low which clears the PMS status bit.

Bit 2: Power-Down (PD). When this bit is set, the LIU and digital logic for this port are powered down and

considered “out of service.” The logic is powered down by stopping the clocks. See the Reset and Power-Down

section in Section 10.3.

0 = Normal operation

1 = Power-down port circuits (default state)

Bit 1: Reset Data Path (RSTDP). When this bit is set, it will force all of the internal data path registers in this port

to their default state. This bit must be set high for a minimum of 100ns and then set back low. See the Reset and

Power-Down section in Section 10.3. Note: The Default State of this bit is 1 (after a general reset (port or global),

this bit will be set to one).

0 = Normal operation

1 = Force all data path registers to their default values

Bit 0: Reset (RST). When this bit is set, it will force all the internal data path and status and control registers

(except this RST bit) of this port to their default state. See the Reset and Power-Down section in Section 10.3. This

bit must be set high for a minimum of 100ns and then set back low. This software bit is logically ORed with the

inverted hardware signal

RST and the GL.CR1.RST bit.

0 = Normal operation

1 = Force all internal registers to their default values

PORT.CR2

Port Control Register 2

(0,2,4,6)42h

Bit #

Name

TLEN

TTS

RMON

TLBO

RESERVED

LM2

LM1

LM0

Default

Bit #

Name

RESERVED

FM2

FM1

FM0

RESERVED

Default

Bit 15: Transmit Line IO Signal Enable (TLEN). This bit is used to enable to transmit line interface output pins

TLCLKn, TPOSn/TDATn and TNEGn.

DS3172 Datasheet(PDF) 137 Page - Dallas Semiconductor

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