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DS3172 Datasheet(PDF) 148 Page - Dallas Semiconductor

Part # DS3172
Description  Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
PDF  232 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3172 Datasheet(HTML) 148 Page - Dallas Semiconductor

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Register Name:
BERT.PCR
Register Description:
BERT Pattern Configuration Register
Register Address:
(0,2,4,6)62h
Bit #
15
14
13
12
11
10
9
8
Name
--
--
--
PTF4
PTF3
PTF2
PTF1
PTF0
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Name
--
QRSS
PTS
PLF4
PLF3
PLF2
PLF1
PLF0
Default
0
0
0
0
0
0
0
0
Bits 12 to 8: Pattern Tap Feedback (PTF[4:0]) – These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored
when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.
Bit 6: QRSS Enable (QRSS) – When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and
PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a
generating polynomial of x
20 + x17 + 1. The output of the pattern generator will be forced to one if the next fourteen
output bits are all zero.
Bit 5: Pattern Type Select (PTS) – When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]) – These five bits control the “length” feedback of the pattern
generator. The “length” feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal,
the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.
Register Name:
BERT.SPR1
Register Description:
BERT Seed/Pattern Register #1
Register Address:
(0,2,4,6)64h
Bit #
15
14
13
12
11
10
9
8
Name
BSP15
BSP14
BSP13
BSP12
BSP11
BSP10
BSP9
BSP8
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Name
BSP7
BSP6
BSP5
BSP4
BSP3
BSP2
BSP1
BSP0
Default
0
0
0
0
0
0
0
0
Bits 15 to 0: BERT Seed/Pattern (BSP[15:0]) – Lower sixteen bits of 32 bits. Register description follows next
register.



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