DS3172 datasheet(150/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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Bit 2: Bit Error Insertion Enable (BEI) – When 0, single bit error insertion is disabled. When 1, single bit error

insertion is enabled.

Bit 1: Transmit Single Error Insert (TSEI) – This bit causes a bit error to be inserted in the transmit data stream if

manual error insertion is disabled (MEIMS = 0) and single bit error insertion is enabled. A 0 to 1 transition causes a

single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If

MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error will be

inserted.

Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit.

When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is

one, changing the state of this bit may cause a bit error to be inserted.

BERT.SR

BERT Status Register

(0,2,4,6)6Ch

Bit #

Name

Bit #

Name

PMS

BEC

OOS

Bit 3: Performance Monitoring Update Status (PMS) – This bit indicates the status of the receive performance

monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS

will be forced low when the LPMU bit (PMUM = 0) or the global or port PMU bit (PMUM=1) goes low.

Bit 1: Bit Error Count (BEC) – When 0, the bit error count is zero. When 1, the bit error count is one or more. This

bit is cleared when the user updates the BERT counters via the PMU bit (BERT.CR).

Bit 0: Out Of Synchronization (OOS) – When 0, the receive pattern generator is synchronized to the incoming

pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.

BERT.SRL

BERT Status Register Latched

(0,2,4,6)6Eh

Bit #

Name

Bit #

Name

PMSL

BEL

BECL

OOSL

Bit 3: Performance Monitoring Update Status Latched (PMSL) – This bit is set when the PMS bit transitions

from 0 to 1.

Bit 2: Bit Error Latched (BEL) – This bit is set when a bit error is detected.

Bit 1: Bit Error Count Latched (BECL) – This bit is set when the BEC bit transitions from 0 to 1.

Bit 0: Out Of Synchronization Latched (OOSL) – This bit is set when the OOS bit changes state.

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