DS3172 datasheet(149/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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BERT.SPR2

BERT Seed/Pattern Register #2

(0,2,4,6)66h

Bit #

Name

BSP31

BSP30

BSP29

BSP28

BSP27

BSP26

BSP25

BSP24

Default

Bit #

Name

BSP23

BSP22

BSP21

BSP20

BSP19

BSP18

BSP17

BSP16

Default

Bits 15 to 0: BERT Seed/Pattern (BSP[31:16]) - Upper 16 bits of 32 bits.

BERT Seed/Pattern (BSP[31:0]) – These 32 bits are the programmable seed for a transmit PRBS pattern, or the

programmable pattern for a transmit or receive repetitive pattern. BSP(31) will be the first bit output on the transmit

side for a 32-bit repetitive pattern or 32-bit length PRBS. BSP(31) will be the first bit input on the receive side for a

32-bit repetitive pattern.

BERT.TEICR

BERT Transmit Error Insertion Control Register

(0,2,4,6)68h

Bit #

Name

Default

Bit #

Name

TEIR2

TEIR1

TEIR0

BEI

TSEI

MEIMS

Default

Bits 5 to 3: Transmit Error Insertion Rate (TEIR[2:0]) – These three bits indicate the rate at which errors are

inserted in the output data stream. One out of every 10

n bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value

of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10

th bit being inverted. A

TEIR[2:0] value of 2 result in every 100

th bit being inverted. Error insertion starts when this register is written to with

a TEIR[2:0] value that is non-zero. If this register is written to during the middle of an error insertion process, the

new error rate will be started after the next error is inserted.

TEIR[2:0]

Error Rate

000

Disabled

001

1 x 10

-1

010

1 x 10

-2

011

1 x 10

-3

100

1 x 10

-4

101

1 x 10

-5

110

1 x 10

-6

111

1 x 10

-7

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