GS12281 datasheet(46/97 Pages) SEMTECH

46 / 97 page

GS12281

Final Data Sheet

Rev.9

PDS-061385

February 2019

46 of 97

Semtech

Proprietary & Confidential

www.semtech.com

Multiple chains of GS12281 devices can share a single SDOUT bus connection to host by

configuring the devices for Bus-Through operation. In such configuration, each chain

requires a separate Chip Select (CS).

Figure 4-12: GSPI_BUS_THROUGH_ENABLE Operation

4.9.4 SCLK Pin

The SCLK pin is the GSPI serial data shift clock input to the device, and must be provided

by the host processor.

Serial data is clocked into the GS12281 SDIN pin on the rising edge of SCLK. Serial data

is clocked out of the device from the SDOUT pin on the falling edge of SCLK (read

operation). SCLK is ignored when CS is HIGH.

The maximum interface clock rate is 27MHz.

4.9.5 Command Word 1 Description

All GSPI accesses are a minimum of 48 bits in length (two 16-bit Command Words

followed by a 16-bit Data Word) and the start of each access is indicated by the

HIGH-to-LOW transition of the chip select (CS) pin of the GS12281.

The format of the Command Words and Data Word are shown in Figure 4-13.

Data received immediately following this HIGH-to-LOW transition will be interpreted as

a new Command Word.

4.9.5.1 R/W bit—B15 Command Word 1

This bit indicates a read or write operation.

When R/W is set to 1, a read operation is indicated, and data is read from the register

specified by the ADDRESS field of the Command Word.

When R/W is set to 0, a write operation is indicated, and data is written to the register

specified by the ADDRESS field of the Command Word.

SDIN pin

SDOUT pin

GSPI_LINK

_DISABLE

BUS_THROUGH_

ENABLE

CS pin

High-Z

Configuration and

Status Register

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