GS12281 datasheet(82/97 Pages) SEMTECH

82 / 97 page

GS12281

Final Data Sheet

Rev.9

PDS-061385

February 2019

82 of 97

Semtech

Proprietary & Confidential

www.semtech.com

PRBS_CHK_

CTRL

RSVD

15:9

R/W

Reserved - do not modify.

CTRL_PRBS_CHECK_



TIMED_CONT_B

8R/W

Selects between timed and continuous

PRBS check mode.

0 = Selects continuous PRBS check

mode.



1 = Selects timed PRBS check mode.

RSVD

7:1

R/W

Reserved - do not modify.

CTRL_PRBS_CHECK_



START

0R/W

Set to 1 by host to start a timed

operation.

Set to 0 by host after completion or

abort of the operation (by the device

due to loss of lock) to tell the device that

PRBS result has been read by the host.

See Section 4.4 for more details on PRBS

checker function.

PRBS_GEN_

CTRL

RSVD

15:10

R/W

Reserved - do not modify.

CTRL_PRBS_GEN_



ENABLE

9R/W

Selects whether the PRBS generator is

enabled or not:

0 = PRBS Generator disabled



1 = PRBS Generator enabled

Note: enabling the PRBS generator does

not automatically override other device

modes such as auto-sleep,

auto-output-mute, auto-output-disable,

etc. These continue to function

normally. The user/host may need to

adjust those settings to ensure the part

will output the PRBS signal.

CTRL_PRBS_GEN_



SIGNAL_SELECT

8R/W

Select output signal from PRBS

generator as either PRBS7 or divided

clock (divided version of the PRBS

generator clock source):

0 = clock divider (using ratio set by

CTRL_PRBS_GEN_CLK_DIVIDER)



1 = PRBS7

CTRL_PRBS_GEN_



CLK_SRC

7:6

R/W

Selects clock source for PRBS generator:

0 = VCO (free running)



1 = Reserved



2 = Reserved



3 = Data reference PLL (CDR recovered

clock)

Table 5-3: Control Register Descriptions (Continued)

Addressh

Name

Parameter Name

Bit

Slice

R/W

Reset

Valueh

Description

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