GS12281 datasheet(64/97 Pages) SEMTECH

64 / 97 page

GS12281

Final Data Sheet

Rev.9

PDS-061385

February 2019

64 of 97

Semtech

Proprietary & Confidential

www.semtech.com

FACTORY_

CDR_

PARAMETERS

RSVD

15:4

R/W

Reserved - do not modify.

PHASE_MODE

3:2

R/W

Set to 3h when using a PRBS7 signal or

similar repetitive short pattern.

CFG_MIN_LBW

R/W

To maximize loop bandwidth of PLL and

consequently IJT of CDR, set this

parameter to 0.

RSVD

R/W

Reserved - do not modify.

PLL_LOOP_

BANDWIDTH_

RSVD

15:13

R/W

Reserved - do not modify.

CFG_PLL_LBW_12G

12:8

R/W

Configure PLL loop bandwidth in terms

of ratio to nominal loop bandwidth 'x'

(see Table 2-3).

11.88Gb/s (12G) loop bandwidth

setting:



0x00 = Reserved - do not use



0x01 = 0.0625x



0x02 = 0.125x



0x03 = 0.1875x



0x04 = 0.25x



0x05 = 0.3125x



0x06 = 0.375x



0x07 = 0.4375x



0x08 = 0.5x



0x09 = 0.5625x



0x0A = 0.625x



0x0B = 0.6875x



0x0C = 0.75x



0x0D = 0.8125x



0x0E = 0.875x



0x0F = 0.9375x



0x10 to 0x1B = Reserved - do not use



0x1C = 1.0x (nominal)



0x1D = 1.0625x



0x1E = 1.125x



0x1F = 1.1875x

RSVD

7:5

R/W

Reserved - do not modify.

CFG_PLL_LBW_6G

4:0

R/W

Configure 5.94Gb/s (6G) PLL loop

bandwidth in terms of ratio to nominal

loop bandwidth 'x' (see Table 2-3).



See CFG_PLL_LBW_12G parameter for

available settings.

Table 5-3: Control Register Descriptions (Continued)

Addressh

Name

Parameter Name

Bit

Slice

R/W

Reset

Valueh

Description

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