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FXLS8964AF Datasheet(PDF) 16 Page - NXP Semiconductors |
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FXLS8964AF Datasheet(HTML) 16 Page - NXP Semiconductors |
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16 / 98 page  NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Objective data sheet Rev. 2 — 30 October 2020 16 / 98 10 I2C digital interface The registers embedded within FXLS8964AF may be accessed using an I2C interface when the INTF_SEL pin is tied to GND. If the VDD supply is not present, the device will be in shutdown mode and any communications on the interface are ignored. When the device is on a common I2C-bus with other slave devices, the VDD supply pin must be left unconnected (high-impedance) when the device supply is turned off to ensure that the internal ESD protection diodes do not become forward biased and prevent the bus from functioning normally (clamping). The I2C slave interface port of FXLS8964AF is compliant with the following three operating modes as defined in UM10204 I2C-bus specification and user manual, Rev. 6 April 2014: • Fast-mode Plus (Fm+) at 1000 kHz • Fast-mode (Fm) at 400 kHz • Standard-mode (Sm) at 100 kHz Table 9. I2C serial interface pin description Pin Name Pin Description SCL I2C serial clock (pull-up resistor is required) SDA I2C serial data (pull-up resistor is required) 10.1 I2C interface characteristics The I2C slave address (7-bit format) is set to 18h when SA0 = 0, and 19h when SA0 = 1. Table 10. FXLS8964AF I2C read and write addresses SA0 I2C write address I2C read address 0 30h (0011 0000b) 31h (0011 0001b) 1 32h (0011 0010b) 33h (0011 0011b) Table 11. I2C slave timing values for Standard-mode (Sm) and Fast-mode (Fm), and Fast-mode Plus (Fm+) I2C Standard- mode[1] I2C Fast-mode[1] I2C Fast-mode Plus[2] Parameter Symbol Min Max Min Max Min Max Unit SCL clock frequency fSCL 0 100 0 400 0 1000 kHz Bus free time between STOP and START conditions tBUF 4.7 — 1.3 — 0.5 — µs Repeated START hold time tHD;STA 4 — 0.6 — 0.26 — µs Repeated START setup time tSU;STA 4.7 — 0.6 — 0.26 — µs STOP condition setup time tSU;STO 4 — 0.6 — 0.26 — µs SDA valid time[3] tVD;DAT — 3.45[4] — 0.9[4] — 0.45[4] µs |
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