FXLS8964AF datasheet(66/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

66 / 98

Field

Description

BUF_MODE[1:0]

Buffer data collection mode:

00: Buffer is disabled.

01: Stream Mode: buffer always contains the most recent 32 samples when overflowed.

The oldest sample data is replaced with new data when the buffer becomes full and a new

sample arrives.

10: Stop Mode: buffer stops accepting new samples when full.

11: Trigger mode: The buffer will operate in circular mode until the trigger event

occurs, collecting up to

BUF_CONFIG2[BUF_WMRK[5:0]] samples; after a

configured trigger event occurs the buffer will continue to accept up to (32-

BUF_

CONFIG2[BUF_WMRK[5:0]]) samples, set the BUF_OVF flag, and stop collecting

further samples. This allows acceleration data to be collected both before and after the

trigger event, with the maximum number of pre-trigger samples defined by the

BUF_

CONFIG2[BUF_WMRK[5:0]] setting. Note that the BUF_OVF flag will be cleared and

the triggered mode re-armed once the host flushes or reads all the buffer contents.

The available trigger sources are the SDCD within- and outside-of-thresholds events,

and orientation change event. These trigger sources are enabled in this register via the

TRIG_SDCD_WT, TRIG_SDCD_OT, and TRIG_ORIENT bits.

BUF_GATE

Output data buffer gate enable:

0: Buffer gate is bypassed (default). Output data buffer is automatically flushed when FX

LS8964AF transitions from WAKE to SLEEP or SLEEP to WAKE modes. This is done to

prevent acceleration data from two different ODR's rates becoming mixed in the output

buffer.

1: The Output data buffer input gate is enabled when transitioning from WAKE to

SLEEP or SLEEP to WAKE modes; the entire buffer contents must be read out or

flushed (

BUF_CONFIG2[BUF_FLUSH] = 1) to allow the further collection of sample

data. Any new sample(s) that arrive before the buffer has been read out or flushed are

discarded, and the BUF_GATE_ERR bit in the

SYS_MODE register is asserted. SYS_

MODE[BUF_GATE_CNT] maintains a count of the number of samples discarded since

the BUF_GATE_ERR flag was asserted.

Although FXLS8964AF will still transition from WAKE to SLEEP or SLEEP to WAKE, the

contents of the FIFO buffer are preserved, and any new data samples are not stored in

the buffer until it is either emptied of flushed by the host application.

Note:

The BUF_GATE_ERR flag will remain asserted as long as the buffer remains un-emptied.

When triggered buffer mode (BUF_MODE = 11b) is selected and

ASLP_COUNT ≥ 1, the

BUF_GATE setting is ignored.

The BUF_GATE bit in 1: Trigger source is enabled, when set, will hold the last data set

stored in the buffer before transitioning to the SLEEP or WAKE modes. After the buffer is

flushed, FXLS8964AF will start accepting new sample data into the buffer at the current

operating mode ODR.

TRIG_SDCD_WT

SDCD within thresholds event buffer trigger enable:

0: Trigger source is disabled (default).

1: Trigger source is enabled

TRIG_SDCD_OT

SDCD outside of thresholds event buffer trigger enable:

0: Trigger source is disabled (default).

1: Trigger source is enabled

TRIG_ORIENT

Orientation change event buffer trigger enable:

0: Trigger source is disabled (default).

1: Trigger source is enabled

The buffer contents are flushed whenever the buffer is disabled (by setting BUF_MODE

= 00b), when

BUF_CONFIG2[BUF_FLUSH] is set, or after an automatic power

FXLS8964AF Datasheet(PDF) 66 Page - NXP Semiconductors

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