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FXLS8964AF Datasheet(PDF) 42 Page - NXP Semiconductors |
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FXLS8964AF Datasheet(HTML) 42 Page - NXP Semiconductors |
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42 / 98 page ![]() NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Objective data sheet Rev. 2 — 30 October 2020 42 / 98 Bit 7 6 5 4 3 2 1 0 Name SX SX SX SX OUT_Y[11:8] Reset — — — — — — — — Access R R R R R R R R Table 29. OUT_Z_LSB and OUT_Z_MSB register (addresses 08h to 09h) with SEN_CONFIG2[LE_BE] = 0 bit allocation Bit 7 6 5 4 3 2 1 0 Name OUT_Z[7:0] Reset — — — — — — — — Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Name SX SX SX SX OUT_Z[11:8] Reset — — — — — — — — Access R R R R R R R R Table 30. OUT_X_LSB and OUT_X_MSB register (addresses 04h to 05h) with SEN_CONFIG2[LE_BE] = 1 bit allocation Bit 7 6 5 4 3 2 1 0 Name OUT_X[11:4] Reset — — — — — — — — Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Name OUT_X[3:0] 0 0 0 0 Reset — — — — — — — — Access R R R R R R R R Table 31. OUT_Y_LSB and OUT_Y_MSB register (addresses 06h to 07h) with SEN_CONFIG2[LE_BE] = 1 bit allocation Bit 7 6 5 4 3 2 1 0 Name OUT_Y[11:4] Reset — — — — — — — — Access R R R R R R R R |
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