FXLS8964AF datasheet(36/98 Pages) NXP

36 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

36 / 98

Auto-increment Address

Name

Type

Address

F_READ = 0

F_READ = 1

Default

Values

BT_MODE =

GND/[VDD]

Comment

ORIENT_THS_REG [1] [5]

R/W

2Ch

2Dh

84h

Orientation detection state change threshold

angle (Portrait/Landscape) and hysteresis

settings.

Sensor data change detection function configuration and status

SDCD_INT_SRC1 [1] [2]

2Dh

2Eh

00h

Sensor Data Change Detection function

outside-of-thresholds event flags source

SDCD_INT_SRC2 [1] [2]

2Eh

2Fh

00h

Sensor Data Change Detection function within

thresholds event flags source register.

SDCD_CONFIG1 [1] [5]

R/W

2Fh

30h

00h/[38h]

Sensor Data Change Detection function

configuration register 1 – Event latch enables

and individual axis enable bits for OT and WT

logic function participation.

SDCD_CONFIG2 [1] [5]

R/W

30h

31h

00h/[D8h]

Sensor Data Change Detection function

configuration register 2 – SDCD function

enable, reference values initialization and

update behavior, relative/absolute operating

mode selection, debounce counter behavior.

Note: only the REF_UPD bit may be set in

Active mode.

SDCD_OT_DBCNT [1] [5]

R/W

31h

32h

00h/[00h]

Sensor Data Change Detection outside of

thresholds condition debounce count value

sdcd_ot_dbcnt[7:0]

SDCD_WT_DBCNT [1] [5]

R/W

32h

33h

00h/[00h]

Sensor Data Change Detection within

thresholds condition debounce count value –

sdcd_wt_dbcnt[7:0]

SDCD_LTHS_LSB [1] [5]

R/W

33h

34h

00h/[C0h]

Sensor Data Change Detection lower

threshold value LSB - sdcd_lths[7:0]

SDCD_LTHS_MSB [1] [5]

R/W

34h

35h

00h/[0Fh]

Sensor Data Change Detection lower

threshold value MSB - sdcd_lths[11:8].

SDCD_UTHS_LSB [1] [5]

R/W

35h

36h

00h/[40h]

Sensor Data Change Detection upper

threshold value LSB - sdcd_uths[7:0]

SDCD_UTHS_MSB [1] [5]

R/W

36h

37h

00h/[00h]

Sensor Data Change Detection upper

threshold value MSB - sdcd_uths[11:8]

SELF_TEST_CONFIG1 [1] [5]

R/W

37h

38h

00h

Self-Test Idle phase duration:

SELF_TEST_CONFIG2 [1] [5]

R/W

38h

39h

00h

Self-Test measurement phase decimation

factor

reserved register 12

R/W

39h

3Ah

00h

Factory reserved register; do not modify

reserved register 13[1]

3Ah

00h

—

Factory reserved register

[1]

Register contents are preserved when a transition from ACTIVE to STANDBY mode occurs. All register contents are lost when a transition from Hibernate

mode or a POR/BOR event occurs.

[2]

[3]

The endianness and L/R justification of these registers is user programmable between little-endian right justified and big-endian (left justified) modes. The

default mode is little-endian, right justified. The endianness and justification is controlled by

SENS_CONFIG3[LE_BE].

[4]

The output data buffer contents become obsolete whenever a transition from STANDBY-to-ACTIVE or STANDBY-to-EXT_TRIG modes occurs.

[5]

SENS_CONFIG1[ACTIVE], SENS_

CONFIG1[RST] and BUF_CONFIG1[BUF_FLUSH] bits that may be set at any time in STANDBY, ACTIVE or EXT_TRIG modes. The ACTIVE bit state

cannot be modified while in EXT_TRIG operating mode.

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