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FXLS8964AF Datasheet(PDF) 25 Page - NXP Semiconductors

Part # FXLS8964AF
Description  3-Axis Low-g Accelerometer
PDF  98 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS8964AF Datasheet(HTML) 25 Page - NXP Semiconductors

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NXP Semiconductors
FXLS8964AF
3-Axis Low-g Accelerometer
FXLS8964AF
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Objective data sheet
Rev. 2 — 30 October 2020
25 / 98
Note: When FXLS8964AF is operated in 3-wire SPI mode - by setting
SENS_CONFIG1[SPI_M] = 1 - the SA0/SPI_MISO pin is always placed in a high
impedance (high-z) state, with the SPI_MISO pin output driver disabled (tri-stated).
Table 13.  Slave timing values
Specifications
Label
Description
Min.
Max.
Unit
fSCLK
SCLK frequency
0
4
MHz
tSCLK
SCLK Period
250
—
ns
tSCLKH
SCLK high time
100
—
ns
tSCLKL
SCLK low time
100
—
ns
tSCS
Setup time for SPI_CS_B signal
125
—
ns
tHCS
Hold time for SPI_CS_B signal
240
—
ns
tHZ
Hold time for SPI_DATA signal transition
back to high-impedance state
—
25
ns
tWCS
Inactive time for SPI_CS_B signal
600
—
ns
tSET
Data setup time for SPI_DATA signal
10
—
ns
tHOLD
Data hold time for SPI_DATA signal
10
—
ns
tDDLY
Data setup time for SPI_DATA signal (output
phase)
—
50
ns
SPI_CS_B
tSCS
SCLK
tSET
SPI_DATA
SPI_MISO
tHOLD
tSCLK
tSCLKH
tSCLKL
tDDLY
tHCS
tWCS
High-Impedance
tHZ
High-Impedance
High-Impedance
Figure 19. SPI timing diagram (3-wire mode)



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