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FXLS8964AF Datasheet(PDF) 45 Page - NXP Semiconductors |
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FXLS8964AF Datasheet(HTML) 45 Page - NXP Semiconductors |
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45 / 98 page ![]() NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Objective data sheet Rev. 2 — 30 October 2020 45 / 98 In big-endian mode (with SENS_CONFIG2[LE_BE] = 1), the output buffer data registers are arranged with the MSB of each axis data stored at the lower register address. The lower nibble(LSB) is stored at the next address, and is left justified. The lower 4 bits of the LSB will always read as '0'. The host software will have to right shift the data by 4 bits (or divide the value by 16) in order to obtain the correct scaling of the acceleration data. If SENS_CONFIG2[F_READ] = 1, the auto increment mechanism will skip over the MSB registers. This will shorten the output data size from 6 bytes to 3 bytes per XYZ sample. When SENS_CONFIG2[F_READ] = 1, the MSB of each axes data will be stored at the LSB address, regardless of the setting made in SENS_CONFIG2[LE_BE]. The output data size may also be reduced using the X/Y/Z_DIS bits located in the SENS_CONFIG5 register. These bits can be used to selectively disable each axis from being read out using the auto-increment mechanism. For example, setting X_DIS will cause the auto-increment mechanism to skip over the BUF_X LSB and MSB registers, thereby shortening the number of bytes to be read from 6 to 4, or from 3 to 2 when F_READ = 1. Note that reading the BUF_STATUS register is not required in order to clear the BUF_WMRK event flag - if the host has mapped more than the BUF_WMRK event flag to the same interrupt pin, the BUF_STATUS register should be used to confirm that a BUF_WMRK event was the source of the interrupt before initiating the burst read operation. Table 35. BUF_X_LSB and BUF_X_MSB registers (addresses 0Ch, 0Dh) with SENS_CONFIG2[LE_BE] = 0 bit allocation Bit 7 6 5 4 3 2 1 0 Name BUF_X[7:0] Reset — — — — — — — — Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Name SX SX SX SX BUF_X[11:8] Reset — — — — — — — — Access R R R R R R R R Table 36. BUF_Y_LSB and BUF_Y_MSB registers (addresses 0Eh, 0Fh) with SENS_CONFIG2[LE_BE] = 0 bit allocation Bit 7 6 5 4 3 2 1 0 Name BUF_Y[7:0] Reset — — — — — — — — Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Name SX SX SX SX BUF_Y[11:8] Reset — — — — — — — — Access R R R R R R R R |
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