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FXLS8964AF Datasheet(PDF) 20 Page - NXP Semiconductors |
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FXLS8964AF Datasheet(HTML) 20 Page - NXP Semiconductors |
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20 / 98 page  NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Objective data sheet Rev. 2 — 30 October 2020 20 / 98 10.1.2.5 I2C data sequence diagrams <Single Byte Read> <Multiple Byte Write> W SP Master Slave <Single Byte Write> Legend ST: Start Condition SR: Repeated Start Condition SP: Stop Condition NACK: No Acknowledge W: Write = 0 ACK: Acknowledge ACK ACK ACK ACK ST Device Address[6:0] W SP Register Address[7:0] ACK ACK ACK <Multiple Byte Read> SP ACK ACK NACK ST Device Address[6:0] W Register Address[7:0] ACK ACK ACK SR Device Address[6:0] R continued ACK ST Device Address[6:0] W Register Address[7:0] ACK ACK SR R ACK SP NACK Data[7:0] Data[7:0] Data[7:0] Data[7:0] Data[7:0] Data[7:0] Data[7:0] Data[7:0] Master Slave Master Slave Master Slave Master Slave Register Address[7:0] Device Address[6:0] ST Device Address[6:0] Figure 11. I2C Data Sequence Diagrams 11 SPI interface The SPI interface is a classical Master/Slave serial port. FXLS8964AF is always considered to be the slave device and thus never initiates communication with the host processor. The SPI interface of FXLS8964AF is compatible with interface mode 00, corresponding to CPOL = 0 and CPHA = 0. For CPOL = 0, the idle value of the clock is zero, and the active value of the clock is 1. For CPHA = 0, data is captured on the clock's rising edge (low to high transition) and data is propagated on the clock's falling edge (high to low transition). 11.1 General SPI operation The SPI_CS_B pin is driven low at the start of a transaction, held low for the duration of the transfer, and then driven high again after the transaction is completed. During a transaction, the master toggles the clock (SCLK). The SCLK polarity is defined as having an idle value that is low, and an active phase that is high (CPOL = 0). Serial input and output data is captured on the clock's rising edge and propagated on the falling edge |
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