FXLS8964AF datasheet(52/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

52 / 98

Field

Description

F_READ

Fast-read mode selection

When this bit is set, the output data format is limited to the most significant byte of the 12-bit sample.

The MSB data will always be stored in the lower address, regardless of the setting made in

SENS_

CONFIG1[LE_BE]. The auto-increment address pointer will automatically skip over the higher

address for each axis' sample when performing a burst read operation of the current output data or

buffered data when the F_READ bit is set.

0: Normal read mode

1: Fast-read mode

13.13 SENS_CONFIG3 register (address 17h)

The SENS_CONFIG3 register is used to set the WAKE and SLEEP ODRs when

operating in Low Power Mode or High Performance Mode, and the decimation factor for

WAKE and SLEEP modes in Flexible Power Mode.

Note: In motion detection mode with BT_MODE=VDD, use of HPM or FPM mode is not

advised. Only the default LPM mode should be used.

Note: When BT_MODE=VDD, maximum recommended ODR is 100 Hz, this is because

when the data ready interrupt is enabled, the interrupt line (INT1) will pulse low for

TPULSE-MOT seconds (

5 ms typ) for every ODR period. Thus, for higher ODRs, the

host will not observe DRDY interrupt pulse at every ODR period.

Table 50. SENS_CONFIG3 register (address 17h) bit allocation

Bit

Name

WAKE_ODR[3:0] / WAKE_DEC[3:0]

SLEEP_ODR[3:0] / SLEEP_DEC[3:0]

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

In HPM and LPM modes, a decimation factor is implicit, as specified in Table 51 and

Table 52, respectively.

In FPM, the decimation factor for WAKE and SLEEP modes is specified via the same bit-

fields (see Table 53 for the available settings), and along with the WAKE and SLEEP idle

time parameter determines the effective ODR.

For example, if

SENS_CONFIG2[WAKE_PM] = 10b, selecting FPM in the WAKE

operating mode, the SENS_CONFIG3 upper nibble is interpreted as the decimation

factor for WAKE mode (WAKE_DEC[3:0]) per Table 53. If a value of 0110b is chosen,

for example, a decimation factor of 64 is selected. If WAKE_IDLE[11:0] is set to 256

(decimal), the effective ODR would be 1 / ((256+1) * (312.5µs) * 64) = 0.195 Hz.

The effective ODR is determined in a similar manner for the SLEEP operating mode

using the SLEEP_DEC[3:0] and the SLEEP_IDLE[11:0] values.

When operating in HPM or LPM with ODR = 3200 Hz, or in FPM with IDLE_TIME = 0,

the first data sample is produced after a time delay greater than 1 ODR period per the

following equation:

TDELAY (s) = 528.5 µs + 0.9984 * (DEC – 1) * (1 / (ODR * DEC))

Note: The IDLE_TIME refers to either WAKE_IDLE[11:0] or SLEEP_IDLE[11:0],

depending on current operating mode.

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