VR4102 datasheet(170/701 Pages) NEC

170 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

170

6.3.10 Parity Error Register (26)

The read/write Parity Error (PErr) register contains the cache data parity bits for cache initialization, cache

diagnostics, or cache error processing.

The PErr register is loaded by the Index_Load_Tag CACHE instruction. All bits of the parity field are valid on the

data cache operation because data cache employs byte parity (1-bit parity for 1 byte). But a LSB of the parity field is

valid on the instruction cache operation because instruction cache employs word parity (1-bit parity for 1 word).

The contents of the PErr register are:

— written into the on-chip data cache on store instructions (instead of the computed parity) when the CE bit of

the Status register is set to 1

— substituted for the computed parity for the CACHE Fill instruction

In the VR4102, parity check is performed only for cache memory.

It is not performed for main memory or peripheral units.

Figure 6-11 shows the format of the PErr register.

Figure 6-11. Parity Error Register Format

Parity

Parity : Specifies the 8-bit parity data to be read from or written to the on-chip cache.

: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

VR4102 Datasheet(PDF) 170 Page - NEC