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VR4102 Datasheet(PDF) 168 Page - NEC |
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VR4102 Datasheet(HTML) 168 Page - NEC |
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168 / 701 page  CHAPTER 6 EXCEPTION PROCESSING 168 6.3.8 WatchLo (18) and WatchHi (19) Registers The VR4102 processor provides a debugging feature to detect references to a selected physical address; load and store instructions to the location specified by the WatchLo and WatchHi registers cause a Watch exception. Figures 5-9 and 5-10 show the format of the WatchLo and WatchHi registers. Figure 5-9. WatchLo and WatchHi Register Format 29 3 2 1 0 31 PAddr0 0 R W 1 1 1 32 0 31 0 WatchLo Register WatchHi Register PAddr0 : Specifies physical address bits 31 to 3. R : If this bit is set to 1, an exception will occur when a load instruction is executed. W : If this bit is set to 1, an exception will occur when a store instruction is executed. 0 : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. |
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