VR4102 datasheet(165/701 Pages) NEC

165 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

165

6.3.6 Cause Register (13)

The 32-bit read/write Cause register holds the cause of the most recent exception.

A 5-bit exception code

indicates one of the causes (see Table 6-2). Other bits holds the detailed information of the specific exception. All

bits in the Cause register, with the exception of the IP1 and IP0 bits, are read-only; IP1 and IP0 are used for software

interrupts. Figure 6-7 shows the fields of this register; Table 6-2 describes the Cause register codes.

Figure 6-7. Cause Register Format

16 15

31 30 29 28

IP(7..0)

ExcCode

: Indicates whether the most recent exception occurred in the branch delay slot (1

→ In delay slot, 0

→ Normal).

: Indicates the coprocessor number in which a Coprocessor Unusable exception occurred.

This field will remain undefined for as long as no exception occurs.

: Indicates whether an interrupt is pending (1

→ Interrupt pending, 0 → No interrupt pending).

IM7

: A timer interrupt.

IM(6:2)

: Ordinary interrupts (Int(4:0)

Note). However, Int4Note never occurs in the VR4102.

IM(1:0)

: Software interrupts. Only these bits cause an interrupt exception, when they are set to 1

by means of software.

Note Int(4:0) are internal signals of the VR4100 CPU core. For details about connection to the on-

chip peripheral units, refer to Chapter 14.

ExcCode : Exception code field (refer to Table 6-2 for details)

: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

VR4102 Datasheet(PDF) 165 Page - NEC