VR4102 datasheet(162/701 Pages) NEC

162 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

162

6.3.4 Compare Register (11)

The Compare register causes a timer interrupt; it maintains a stable value that does not change on its own.

When the value of the Count register (see 6.3.3) equals the value of the Compare register, the IP(7) bit in the

Cause register is set. This causes an interrupt as soon as the interrupt is enabled.

Writing a value to the Compare register, as a side effect, clears the timer interrupt request.

For diagnostic purposes, the Compare register is a read/write register. Normally, this register should be only

used for a write. Figure 6-4 shows the format of the Compare register.

Figure 6-4. Compare Register Format

Compare

Compare: Value that is compared with the count value of the Count register

6.3.5 Status Register (12)

The Status register is a read/write register that contains the operating mode, interrupt enabling, and the

diagnostic states of the processor. Figure 5-5 shows the format of the Status register. Figure 5-6 shows the details

of the Diagnostic Status (DS) field. All DS field bits other than the TS bit are writable.

Figure 6-5. Status Register Format

29 28 27 26 25 24

16 15

CU0

IM (7:0)

KX SX UX

KSU

ERL

EXL

CU0

: Enables/disables the use of the coprocessor (1

o Enabled, 0 o Disabled).

CP0 can be used by the kernel at all times.

: Reserved for future use. Write 0 in a write operation. When this bit is read, 0 is read.

: Enables/disables reversing of the endian setting in User mode (0

o Disabled, 1 o Enabled). This bit

must be set to 0 since the VR4102 supports the little-endian order only.

: Diagnostic Status field (see Figure 6-6).

: Interrupt Mask field used to enable/disable interrupts (0

o Disabled, 1 o Enabled). This field consists

of 8 bits that are used to control eight interrupts. The bits are assigned to interrupts as follows:

IM7

: Masks a timer interrupt.

IM(6:2) : Mask ordinary interrupts (Int(4:0)

Note). However, Int4Note never occur in the VR4102.

IM(1:0) : Mask software interrupts or Cause register IP(1:0).

Note

Int(4:0) are internal signals of the VR4100 CPU core. For details about connection to the on-

chip peripheral units, refer to Chapter 14.

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