VR4102 datasheet(160/701 Pages) NEC

160 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

160

6.3.1 Context Register (4)

The Context register is a read/write register containing the pointer to an entry in the page table entry (PTE) array

on the memory; this array is a table that stores virtual-to-physical address translations. When there is a TLB miss,

the operating system loads the unsuccessfully translated entry from the PTE array to the TLB. The Context register

is used by the TLB Refill exception handler for loading TLB entries. The Context register duplicates some of the

information provided in the BadVAddr register, but the information is arranged in a form that is more useful for a

software TLB exception handler. Figure 6-1 shows the format of the Context register.

Figure 6-1. Context Register Format

(a) 32-bit mode

PTEBase

BadVPN2

(b) 64-bit mode

PTEBase

BadVPN2

PTEBase : The PTEBase field is a read/write field. It is used by software as the pointer to the base address

of the PTE table in the current user address space.

BadVPN2 : The BadVPN2 field is written by hardware if a TLB miss occurs. This field holds the value (VPN2)

obtained by halving the virtual page number of the most recent virtual address for which

translation failed.

: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

The 21-bit BadVPN2 field contains bits 31-11 of the virtual address that caused the TLB miss; bit 10 is excluded

because a single TLB entry maps to an even-odd page pair. For a 1-Kbyte page size, this format can directly

address the pair-table of 8-byte PTEs. When the page size is 4 Kbytes or more, shifting or masking this value

produces the correct PTE reference address.

VR4102 Datasheet(PDF) 160 Page - NEC