VR4102 datasheet(163/701 Pages) NEC

163 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

163

: Enables 64-bit addressing in Kernel mode (0

o 32-bit, 1 o 64-bit). If this bit is set, an XTLB Refill

exception occurs if a TLB miss occurs in the Kernel mode address space.

: Enables 64-bit addressing and operation in Supervisor mode (0

o 32-bit, 1 o 64-bit). If this bit is

set, an XTLB Refill exception occurs if a TLB miss occurs in the Supervisor mode address space.

UX:

: Enables 64-bit addressing and operation in User mode (0

o 32-bit, 1 o 64-bit). If this bit is set, an

XTLB Refill exception occurs if a TLB miss occurs in the User mode address space.

KSU

: Sets and indicates the operating mode (10

o User, 01 o Supervisor, 00 o Kernel).

ERL

: Sets and indicates the error level (0

o Normal, 1 o Error).

EXL

: Sets and indicates the exception level (0

o Normal, 1 o Exception).

: Sets and indicates interrupt enabling/disabling (0

o Disabled, 1 o Enabled).

Figure 6-6. Status Register Diagnostic Status Field

BEV

: Specifies the base address of a TLB Refill exception vector and common exception vector (0

Normal, 1

o Bootstrap).

: Occurs the TLB to be shut down (read-only) (0

o Not shut down, 1 o Shut down). This bit is used to

avoid any problems that may occur when multiple TLB entries match the same virtual address. After

the TLB has been shut down, reset the processor to enable restart. Note that the TLB is shut down

even if a TLB entry matching a virtual address is marked as being invalid (with the V bit cleared).

: Occurs a Soft Reset or NMI exception (0

o Not occurred, 1 o Occurred).

: CP0 condition bit (0

o False, 1 o True). This bit can be read and written by software only; it cannot

be accessed by hardware.

: When CE = 1, the contents of the PErr register are written to the check bits of the cache (See 6.3.10)

: Specifies whether a cache parity error causes an exception (0

o Enable parity check, 1 o Disable

parity check).

: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

The status register has the following fields where the modes and access status are set.

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