VR4102 datasheet(164/701 Pages) NEC

164 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

164

(1) Interrupt enable

Interrupts are enabled when all of the following conditions are true:

— IE is set to 1.

— EXL is cleared to 0.

— ERL is cleared to 0.

— The appropriate bit of the IM is set to 1.

(2) Operating modes

The following Status register bit settings are required for User, Kernel, and Supervisor modes.

— The processor is in User mode when KSU = 10, EXL = 0, and ERL = 0.

— The processor is in Supervisor mode when KSU = 01, EXL = 0, and ERL = 0.

— The processor is in Kernel mode when KSU = 00, EXL = 1, or ERL = 1.

(3) 32- and 64-bit modes

The following Status register bit settings select 32- or 64-bit operation for User, Kernel, and Supervisor

operating modes. Enabling 64-bit operation permits the execution of 64-bit opcodes and translation of 64-bit

addresses. 64-bit operation for User, Kernel and Supervisor modes can be set independently.

— 64-bit addressing for Kernel mode is enabled when KX bit = 1. 64-bit operations are always valid in Kernel

mode.

— 64-bit addressing and operations are enabled for Supervisor mode when SX bit = 1.

— 64-bit addressing and operations are enabled for User mode when UX bit = 1.

(4) Kernel address space accesses

Access to the kernel address space is allowed when the processor is in Kernel mode.

(5) Supervisor address space accesses

Access to the supervisor address space is allowed when the processor is in Supervisor or Kernel mode.

(6) User address space accesses

Access to the user address space is allowed in any of the three operating modes.

(7) Status after reset

The contents of the Status register are undefined after resets, except for the following bits.

x TS and SR are cleared to 0.

x ERL and BEV are set to 1.

x SR is 0 after Cold reset, and is 1 after Soft reset or NMI interrupt.

Remark

Cold reset and Soft reset are CPU core reset (see 7.4 RESET OF THE CPU CORE). For the reset of

all the VR4102 including peripheral units, refer to CHAPTER 7 INITIALIZATION INTERFACE and

CHAPTER 15 PMU.

VR4102 Datasheet(PDF) 164 Page - NEC