VR4102 datasheet(157/701 Pages) NEC

157 / 701 page

157

CHAPTER 6 EXCEPTION PROCESSING

This chapter describes CPU exception processing, including an explanation of hardware that processes

exceptions, followed by the format and use of each CPU exception register.

The chapter concludes with a description of each exception’s cause, together with the manner in which the CPU

processes and services each exception.

6.1 HOW EXCEPTION PROCESSING WORKS

The processor receives exceptions from a number of sources, including translation lookaside buffer (TLB) misses,

arithmetic overflows, I/O interrupts, and system calls. When the CPU detects an exception, the normal sequence of

instruction execution is suspended and the processor enters Kernel mode (see Chapter 5 for a description of system

operating modes).

The processor then disables interrupts and transfers control for execution to the exception handler (located at a

specific address as an exception handling routine implemented by software). The handler saves the context of the

processor, including the contents of the program counter, the current operating mode (User or Supervisor), statuses,

and interrupt enabling. This context is saved so it can be restored when the exception has been serviced.

When an exception occurs, the CPU loads the Exception Program Counter (EPC) register with a location where

execution can restart after the exception has been serviced. The restart location in the EPC register is the address

of the instruction that caused the exception or, if the instruction was executing in a branch delay slot, the address of

the branch instruction immediately preceding the delay slot.

The VR4102 processor supports a Supervisor mode and fast TLB refill for all address spaces. The VR4102 also

provides the following functions:

— Interrupt enable (IE) bit

— Operating mode (User, Supervisor, or Kernel)

— Exception level (normal or exception is indicated by the EXL bit in the Status register)

— Error level (normal or error is indicated by the ERL bit in the Status register).

Interrupts are enabled when the following conditions are satisfied:

(1) Interrupt enable

An interrupt is enabled when the following conditions are satisfied.

x Interrupt enable bit (IE) = 1

x EXL bit = 0, ERL bit = 0

x Corresponding IM field bits in the Status register = 1

VR4102 Datasheet(PDF) 157 Page - NEC