VR4102 datasheet(153/701 Pages) NEC

153 / 701 page

CHAPTER 5 MEMORY MANAGEMENT SYSTEM

153

5.5.9 Virtual-to-Physical Address Translation

During virtual-to-physical address translation, the CPU compares the 8-bit ASID (and while the Global bit, G, is

not set to 1) of the virtual address to the ASID of the TLB entry to see if there is a match. One of the following

comparisons are also made:

— In 32-bit mode, the high-order bitsNote of the 32-bit virtual address are compared to the contents of the VPN2

(virtual page number divided by two) of each TLB entry.

— In 64-bit mode, the high-order bitsNote of the 64-bit virtual address are compared to the contents of the R and

the VPN2 (virtual page number divided by two) of each TLB entry.

If a TLB entry matches, the physical address and access control bits (C, D, and V) are retrieved from the

matching TLB entry. While the V bit of the entry must be set to 1 for a valid address translation to take place, it is

not involved in the determination of a matching TLB entry.

Figure 5-20 illustrates the TLB address translation flow.

Note The number of bits differs from page sizes. The table below shows the examples of high-order bits of the

virtual address in page size of 256 Kbytes and 1 Kbytes.

Page size

Mode

256 Kbytes

1 Kbytes

32-bit mode

bits 31 to 19

bits 31 to 11

64-bit mode

bits 63, 62, 39 to 19

bits 63, 62, 39 to 11

VR4102 Datasheet(PDF) 153 Page - NEC