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VR4102 Datasheet(PDF) 150 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 150 Page - NEC

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CHAPTER 5 MEMORY MANAGEMENT SYSTEM
150
5.5.6 Config Register (16)
The Config register indicates and specifies various configuration options selected on VR4102 processors.
Some configuration options, as defined by the EC and BE fields, are set by the hardware during Cold Reset and
are included in the Config register as read-only status bits for the software to access. Other configuration options
(AD, EP, and K0 fields) can be read/written and controlled by software; on Cold Reset these fields are undefined.
Since only a subset of the VR4000 options are available in the VR4102, some bits are set to constants (e.g., bits
14:13) that were variable in the VR4000. The Config register should be initialized by software before caches are
used. Figure 5-17 shows the format of the Config register.
Figure 5-17. Config Register Format
1
1
1
23
5
1
1
22
17
18
15
16
14
1
3
4
28
30
24
27
31
0
EC
EP
AD
0
1
0
BE
1
1
13
0
1
12
CS
3
11
9
IC
3
8
6
DC
3
5
3
0
3
2
0
K0
EC : System interface clock ratio (read only)
000
o Processor clock frequency divided by 2
Others
o Reserved
EP : Transfer data pattern (cache write-back pattern)
0000
o DD: 1 word/1 cycle
Others
o Reserved
AD : Accelerate data mode setting
0
o VR4000 Series compatible mode
1
o Reserved
BE : BigEndianMem. Indicates endian.
0
o Little endian
1
o Reserved
CS : Cache size mode indication
0
o Reserved
1
o Cache of small capacity
IC : Instruction cache size indication. The size is 2
(10+IC) bytes when CS bit is set to 1.
2
o 4 Kbytes
Others
o Reserved
DC : Data cache size indication. The size is 2
(10+DC) bytes when CS bit is set to 1.
0
o 1 Kbytes
Others
o Reserved
K0 : kseg0 cache coherency algorithm
010
o Uncached
Others
o Cached
1: 1 is returned when it is read.
0: 0 is returned when it is read.



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