VR4102 datasheet(152/701 Pages) NEC

152 / 701 page

CHAPTER 5 MEMORY MANAGEMENT SYSTEM

152

5.5.8 Cache Tag Registers (TagLo (28) and TagHi (29))

The TagLo and TagHi registers are 32-bit read/write registers that hold the primary cache tag and parity during

cache initialization, cache diagnostics, or cache error processing. The Tag registers are written by the CACHE and

MTC0 instructions.

The P fields of these registers are ignored on Index Store Tag operations by the CACHE instruction. Parity is

computed by the store operation. Figure 5-19 shows the format of these registers.

Figure 5-19. TagLo and TagHi Registers

PTagLo

’ P

PTagLo

Instruction

cache

Data cache

Tag Hi

PTagLo: Specifies physical address bits 31 to 10.

: Valid bit

: Dirty bit. However, this bit is defined only for the compatibility with the VR4000 Series processors,

and does not indicate the status of cache memory in spite of its readability and writability. This bit

cannot change the status of cache memory.

: Write-back bit (set if cache line has been updated)

W’

: Even parity for the write-back bit

: Even parity bit for primary cache tag

: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

VR4102 Datasheet(PDF) 152 Page - NEC