VR4102 datasheet(229/701 Pages) NEC

229 / 701 page

CHAPTER 8 CACHE MEMORY

229

Figure 8-22. Data Integrity on Writeback & Refill Flow

Erroneous bit

EOD?

Writeback

Data Parity

OK, DE = 1 or

ERL = 1

OK, DE = 1

or ERL = 1

Error

Writeback

Data Parity

EOD?

Yes

Writeback

to memory

Bus Error

Exception

Cache line

Invalidate

Error existed in

refill data

Erroneous

bit = 0

Erroneous

bit = 1

Refill start

Writeback

Data Parity

Write data

to cache

Yes

Error existed in

writeback data

OK, DE = 1

or ERL = 1

Cache Error

Exception

Error existed in

writeback data

Remark Write-back Procedure:

On a store miss write-back, data tag and tag parity are checked and data parity is transferred to the write

buffer. Byte parity is generated for the physical address and transferred to write buffer. If an error is

detected on the data field, the write back is not terminated; the erroneous data is still written out. If an

error is detected in the tag field, the write-back bus cycle is not issued. In both cases a cache error

exception is taken.

During a Cache operation, cache data may not be checked in some cases, but tag parity is always

checked. At that time, if a tag parity error occurs, the Cache Error exception is taken and the operation is

not permitted to complete.

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