VR4102 datasheet(232/701 Pages) NEC

232 / 701 page

CHAPTER 9 CPU CORE INTERRUPTS

232

9.3 SOFTWARE INTERRUPTS GENERATED IN CPU CORE

Software interrupts generated in the CPU core are acknowledged by setting bits 1 and 0 of the IP (interrupt

pending) field in the Cause register. These may be written by software, but there is no hardware mechanism to set

or clear these bits.

After the processing of a software interrupt exception, corresponding bit of the IP field in the Cause register must

be cleared before returning to ordinary routine or enabling multiple interrupts.

These interrupts are maskable through the IM(1:0), IE, and EXL fields of the Status register.

9.4 TIMER INTERRUPT

The timer interrupt uses bit 15 of the Cause register, which is bit 7 of the IP (interrupt pending) field. This bit is

automatically set whenever the value of the Count register equals the value of the Compare register, to acknowledge

an interrupt request. This interrupt is maskable by setting IM7 of the Status register.

9.5 ASSERTING INTERRUPTS

9.5.1 Detecting Hardware Interrupts

Figure 9-2 shows how the hardware interrupt request is detected through the Cause register.

— The timer interrupt signal, IP7, is directly readable as bit 15 of the Cause register.

— Bits 4:0 of the Interrupt register are bit-wise ORed with the current value of the Int(4:0) signals and the result is

directly readable as bits 14:10 of the Cause register.

IP(1:0

) of the Cause register, which are described in Chapter 6, are software interrupts. There is no hardware

mechanism for setting or clearing the software interrupts.

VR4102 Datasheet(PDF) 232 Page - NEC