VR4102 datasheet(234/701 Pages) NEC

234 / 701 page

CHAPTER 9 CPU CORE INTERRUPTS

234

9.5.2 Masking Interrupt Signals

Figure 9-3 shows the masking of the CPU core interrupt signals.

— Cause register bits 15 to 8 (IP7 to IP0) are AND-ORed with Status register interrupt mask bits 15 to 8 (IM7 to

IM0) to mask individual interrupts.

— Status register bit 0 is a global Interrupt Enable bit (IE). It is ANDed with the output of the AND-OR logic to

produce the CPU core interrupt signal. The EXL bit in the Status register also enables these interrupts.

Figure 9-3. Masking of the CPU Core Interrupts

IM0

IM1

IM2

IM3

IM4

IM5

IM6

IM7

IP0

IP1

IP2

IP3

IP4

IP5

IP6

IP7

Status register

SR (0)

Status register

SR (15:8)

Cause register

(15:8)

Software interrupts

generated in CPU core

Ordinary

interrupts

Timer interrupt

AND-OR

logic

AND logic

CPU core

interrupt

Bit

Function

Setting

Interrupt enable for all interrupts

1: Enable

0: Disable

IM (7:0)

Interrupt mask

1: Enable for individual bits

0: Disable for individual bits

IP (7:0)

Interrupt request

1: Pending request for individual bits

0: No pending for individual bits

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