VR4102 datasheet(237/701 Pages) NEC

237 / 701 page

CHAPTER 10 BCU (BUS CONTROL UNIT)

237

(2/2)

Bit

Name

Function

D[7]

Reserved

Write 0 when writing. 0 is returned after a read.

D[6]

ROMWEN2

This enables flash memory write and issues a flash memory register read-only bus

cycle for the ROM space in banks 3 and 2 (16-bit mode) or in bank 1 (32-bit mode).

1 : Enable (Not affected by PAGEROM2)

0 : Prohibit

D[5]

Reserved

Write 0 when writing. 0 is returned after a read.

D[4]

ROMWEN0

This enables flash memory write and issues a flash memory register read-only bus

cycle for the ROM space in banks 1 and 0 (16-bit mode) or in bank 0 (32-bit mode).

1 : Enable (Not affected by PAGEROM0)

0 : Prohibit

D[3..2]

Reserved

Write 0 when writing. 0 is returned after a read.

D[1]

BUSHERREN

This is the bus timeout detection enable bit, which is used when a bus hold has been

received.

1 : Performs timeout detection when a bus hold has been received.

0 : Does not perform timeout detection when a bus hold has been received.

D[0]

RSTOUT

RSTOUT control bit

1 : High level

0 : Low level

This register is used to set parameters such as the bus interface’s bus cycle.

For the setting of the PAGEROM2 and ROMWEN2 bits, the target ROM area differs depending on a data bus

mode. The access target ROM area is banks 3 and 2 in 16-bit data bus mode, and bank 1 in 32-bit data bus mode.

For the setting of the PAGEROM0 and ROMWEN0 bits, the target ROM area differs depending on the data bus

mode. The access target ROM area is banks 1 and 0 in 16-bit data bus mode, and bank 0 in 32-bit data bus mode.

When a timeout is detected while the BUSHERREN bit is set to 1, the BERRST bit of the BCUERRSTREG

from the external bus master.

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