VR4102 datasheet(240/701 Pages) NEC

240 / 701 page

CHAPTER 10 BCU (BUS CONTROL UNIT)

240

(2/2)

Bit

Name

Function

D[6..4]

WISAA[2..0]

System bus access speed

111 : RFU. Operation is not guaranteed when this value has been set.

110 : RFU. Operation is not guaranteed when this value has been set.

101 : 3TClock

Note

100 : 4TClock

Note

011 : 5TClock

010 : 6TClock

001 : 7TClock

000 : 8TClock

D[3]

Reserved

Write 0 when writing. 0 is returned after a read.

D[2..0]

WROMA[2..0]

ROM access speed

111 : 2TClock

110 : 3TClock

101 : 4TClock

100 : 5TClock

011 : 6TClock

010 : 7TClock

001 : 8TClock

000 : 9TClock

Note When the WISAA [2:0] bits are set to 101 or 100, the AC characteristics between BUSCLK and the system

bus interface signals (ADD [25:0], SHB#, MEMR#, MEMW#, IOR#, and IOW#) are not guaranteed.

This register is used to set the access speed for the LCD, system bus, page ROM, and ROM.

The lowest speed is set when “0” is set to all of the following bits: WLCD/M[2..0], WPROM[1..0], WISAA[2..0],

and WROMA[2..0]. Setting “1” to all of these bits sets the highest speed.

The value set to WPROM[1..0] is valid only when “1” has been set to the PAGEROM bit in BCUCNTREG.

VR4102 Datasheet(PDF) 240 Page - NEC