VR4102 datasheet(231/701 Pages) NEC

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CHAPTER 9 CPU CORE INTERRUPTS

Four types of interrupt are available on the CPU core. These are:

— one non-maskable interrupt, NMI

— five ordinary interrupts

— two software interrupts

— one timer interrupt

These are described in this chapter.

9.1 NON-MASKABLE INTERRUPT (NMI)

The non-maskable interrupt request signal is acknowledged by asserting the NMI signal (internal), forcing the

processor to branch to the Reset Exception vector. This NMI signal is latched into an internal register at the rising

edge of MasterOut, as shown in Figure 9-1.

NMI only takes effect when the processor pipeline is running.

This interrupt cannot be masked.

Figure 9-1 shows the internal derivation of the NMI signal. The NMI signal is latched into an internal register at

the rising edge of MasterOut. The latched NMI signal is inverted and then transmitted as an NMI request.

Figure 9-1. Non-maskable Interrupt Signal

NMI request

NMI signal

MasterOut

(Internal register)

9.2 ORDINARY INTERRUPTS

Ordinary interrupts are set by asserting the Int(4:0) signals (internal).

However, Int4 never occur on the

VR4102.

These interrupts can be masked with the IM(6..2), IE, and EXL fields of the Status register.

VR4102 Datasheet(PDF) 231 Page - NEC