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VR4102 Datasheet(PDF) 257 Page - NEC |
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VR4102 Datasheet(HTML) 257 Page - NEC |
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257 / 701 page  CHAPTER 10 BCU (BUS CONTROL UNIT) 257 Figure 10-7 illustrates 2-byte access when sampling IOCHRDY at high level. If the system bus access time has been set as three TClocks (WISAA[2:0] = 101), the bus cycle will end after waiting for at least 3 TCLocks (Tisa periods) after the ready signal is sampled using IOCHRDY. Sampling of the IOCHRDY signal occurs at the rising edge of the TClock that follows the second or subsequent Tisa period. Figure 10-7. 2-byte Access when Sampling IOCHRDY at High Level Using 16-bit Bus (WISAA[2:0] = 101) Tisa Tisa Tisa TClock(Internal) ADD[25:0] SHB# IOCS16# MEMCS16# IOR#/IOW# MEMR#/MEMW# IOCHRDY ZWS# DATA[15:0] (Write) DATA[15:0] (Read) L Remark The dotted lines indicate high impedance. |
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